1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including an operation test circuit and an operation test method thereof.
2. Related Background Art
Hitherto, an operation test of an semiconductor integrate circuit (hereinafter referred to as an LSI) has been generally performed by supplying an operation test clock signal to the LSI by an external LSI tester.
Recently, however, the operation performance of the LSI has achieved further development, and consequently the frequency of the clock signal supplied from the external LSI tester and an operating frequency in an actual operation become widely different, whereby the operation test of the LSI on the assumption of the actual operation is becoming more and more difficult.
Against this background, an operation test circuit for apparently realizing an operation test by a high-frequency clock signal by using a relatively low-frequency operation test clock signal is proposed (for example, see pages 3 and 4 and FIG. 1 and FIG. 3 of Japanese Patent No. 2953435 which corresponds to Laid-Open Patent Publication No. H10-339769).
FIG. 10 is a diagram showing the configuration of a related operation test circuit. A first and second flip-flops 102 and 103 are provided at both ends of a path, which is to be subjected to an operation test, of a circuit under test 101. Evaluation data D is inputted to the circuit under test 101 via the first flip-flop 102, and output data D′ is outputted therefrom via the second flip-flop 103. Moreover, the evaluation data D, a normal clock C, and a test clock C2 are inputted to each of the first and second flip-flops 102 and 103. The circuit under test 101 here is, for example, a logic circuit.
The first and second flip-flops 102 and 103 are each composed of a master latch and a slave latch, and at a point in time when the logical value of at least one of the normal clock C and the test clock C2 changes from a state of 0 to a state of 1, the evaluation data D is inputted and held in the master latch, whereas at a point in time when the normal clock C changes to the logical value 1, the evaluation data D is outputted via the slave latch. Namely, in a normal operation, the first and second flip-flops 102 and 103 operate as one-phase synchronous flip-flops by maintaining the test clock C2 at the logical value 0, whereas in an operation test, they operate as two-phase synchronous flip-flops by controlling the normal clock C and the test clock C2, whereby the master latch and the slave latch can be controlled separately.
Now, the operation of these flip-flops when the normal clock C and the test clock C2 are inputted at timing shown in FIG. 11 will be considered.
First, attention is focused on the operation of the former-stage flip-flop 102. When the test clock C2 rises from the logical value 0 to the logical value 1 at a point in time t11, the evaluation data D is inputted to the master latch and held therein. Then, when the normal clock C rises at a point in time t12 later than the rising edge of the test clock C2, the evaluation data D held in the master latch is outputted from the slave latch and inputted to a path inside the circuit under test 101 which is to be subjected to the operation test. Next, the operation of the latter-stage flip-flop 103 of the path to be tested will be considered. The evaluation data D is inputted to the master latch when the test clock C2 rises again at a point in time t13.
From the aforementioned operations of the flip-flops, it is understood that the evaluation data D is inputted to the path to be tested at the point in time t12 and outputted therefrom at the point in time t13. When viewed from the path to be tested, this case can be substantially regarded as the same as a case where the flip-flops are operated by a clock with a time interval between the point in time t12 and the point in time t13 as a period. The time interval between the point in time t12 and the point in time t13 is shorter than an actual clock period, and hence it becomes possible to apparently realize the operation test by a high-frequency clock signal by using a relatively low-frequency operation test clock signal.
However, the object of the aforementioned related operation test circuit is only to apparently realize the operation test by the high-frequency clock signal by using the relatively low-frequency clock signal. Therefore, a maximum operating frequency fmax at which the circuit to be tested normally operates cannot be found out.
Moreover, in the aforementioned related operation test circuit, only one path to be evaluated is fixed by positions where two-phase synchronous flip-flops are provided, which cannot cope with a case where the path to be evaluated needs to be changed in the operation test.